This invention pertains to digital data processing and compiler systems. More particularly, this invention relates to techniques for performing an estimation of an optimized assembly code from the C code of an application that is delivered to a C compiler.
The programming of digital signal processor (DSP) applications in high level languages such as C is becoming more prevalent as applications become increasingly more complex. However, current DSP C compilers are generally unable to exploit numerous DSP specific architectural features when attempting to produce efficient assembly code. Therefore, in order to respect tight real-time constraints, programmers commonly write DSP code by hand. However, the programming of such code in assembly language has become increasingly difficult since DSP applications are becoming larger and more complex. Furthermore, the writing of efficient assembly code for new DSP architectures, such as for a Very Long Instruction Word (VLIW) processor, presents a very challenging task.
A tool is provided for estimating an optimized assembly code from the C code of an application. An ability is provided to locate computationally intensive parts of the application. Furthermore, the tool provides a metric of the quality of the produced assembly code. More particularly, an estimation of a hand-written assembly code is generated from an intermediate description (RTL) of an application.
According to one aspect, an assembly code performance evaluation apparatus is provided which includes a host computer, a target digital signal processor (DSP) compiler, and a performance estimation program. The host computer includes processing circuitry, memory and a host compiler to use test sequences and generate dynamic information. The target digital signal processor compiler communicates with the processing circuitry. The performance estimation program is implemented on the host processing circuitry and is operative to annotate application source code and to generate an estimation of an optimized assembly code.
According to another aspect, an assembly code performance evaluation apparatus includes a host computer, a target digital signal processor (DSP) compiler, and a performance estimation program. The host computer includes processing circuitry, memory and a host compiler. The host compiler is operative to execute the program using test sequences and to generate dynamic information. The target digital signal processor (DSP) compiler communicates with the processing circuitry. The performance estimation program is implemented on the processing circuitry and is operative to annotate application source code and to generate an estimation of an optimized assembly code.
According to yet another aspect, a method is provided for evaluating performance of an optimized DSP assembly code. The method includes: providing an application C source code; providing at least one test sequence to generate dynamic information; annotating the application source code with the dynamic information; and generating an estimation of an optimized assembly code.
According to even another aspect, a method is provided for evaluating performance of assembly code. The method includes: providing a target compiler; providing a C code annotated with dynamic information based upon execution of the C code with test sequences on a host computer; generating an RTL intermediate representation of the application; defining a set of rewriting rules; applying the set of rewriting rules to the RTL intermediate representation; and generating an estimation of an optimized assembly code.